With a fail-safe on-delay circuit, an error wherein the delay time is shortened due to a fault is not permitted. Heretofore, with on-delay circuits it has been common to use a counter circuit as a timing circuit for setting the delay time. With a counter circuit however there are problems for example in that the frequency of the clock signal used for timing can increase with a malfunction so that the delay time is shortened, or that if the circuit faults, an output signal can be generated although an input signal is not being applied.
In order to solve such problems, there has been proposed (Japanese Unexamined Patent Publication No. 2-141122) a fail-safe on-delay circuit which uses in the timing circuit, a PUT oscillation circuit which uses a programmable uni-junction transistor (referred to hereunder as PUT). The construction of the fail-safe on-delay circuit is such that a delay output is generated on receipt of an output signal from the PUT oscillation circuit.
FIG. 15 shows such a conventional basic on-delay circuit which uses a PUT oscillation circuit.
In FIG. 15, the on-delay circuit comprises a PUT oscillation circuit 1, and a self hold circuit 2 which produces an output on receipt of an output signal of a predetermined level from the PUT oscillation circuit 1, and self holds the output. The PUT oscillation circuit 1 comprises; resistors R.sub.1.about.R.sub.4, a capacitor C.sub.1, and a PUT. The self hold circuit 2 comprises a logical product circuit 3 having two signal input terminals a, b, and a rectifying circuit 4 and a feed back resistor Rf for feeding back an output from the logical product circuit 3 to the second terminal b so that the output is self held.
The operation of the on-delay circuit will now be described with reference to the operation time chart shown in FIG. 16.
When an input signal V.sub.IN is input to the PUT oscillation circuit 1, then at first, the PUT oscillation circuit 1 becomes condition A. In condition A, the PUT is off so that the capacitor C.sub.1 of the PUT oscillation circuit 1 is gradually charged and the anode terminal voltage V.sub.A rises. Once the capacitor C.sub.1 has been charged to a predetermined voltage level (a gate terminal voltage V.sub.G) the PUT comes on, giving condition B. In condition B, the anode terminal and the cathode terminal, and the gate terminal and the cathode terminal of the PUT are short circuited. Hence the charge stored in the capacitor C.sub.1 is discharged via the PUT, the anode terminal voltage V.sub.A drops, and an anode current i.sub.A and a gate current i.sub.G flow, producing a cathode current i.sub.K, so that a cathode terminal voltage V.sub.K rises. When the rising pulse voltage signal of the cathode terminal voltage V.sub.K is input to the second terminal b of the logical product circuit 3, an output signal is produced from the logical product circuit 3 which has the input signal V.sub.IN already applied to the first terminal a. This output signal is fed back to the second terminal b via the rectifying circuit 4 and the feedback resistor Rf, so that the output signal from the logical product circuit 3 is self held. Hence an output signal continues to be produced until the input signal V.sub.IN is cancelled. In this way, an output signal Z is produced from the self hold circuit 2 as a delay output signal for the on-delay circuit, delayed by a predetermined time .tau..sub.1 from after applying the input signal V.sub.IN to the PUT oscillation circuit 1, based on a timing output signal from the PUT oscillation circuit 1.
Once the capacitor C.sub.1 has been discharged to a certain level, the PUT again goes off, and the PUT oscillation circuit 1 again becomes condition A. While the input signal V.sub.IN is being applied, the PUT oscillation circuit 1 switches back and forth between condition A and condition B, while when the input signal V.sub.IN is cancelled, the PUT oscillation circuit 1 becomes a condition C existing prior to applying the input signal V.sub.IN. In FIG. 15, symbol i.sub.B2 denotes a bias current flowing via the resistor R.sub.4.
With the construction however, as with the conventional on-delay circuit shown in FIG. 15 where after a predetermined time .tau..sub.1 from inputting the input signal V.sub.IN, only the pulse voltage signal produced at the cathode terminal of the PUT is input directly to the second terminal b of the logical product circuit 3, then if for example during timing, a short circuit fault occurs between the gate terminal and the cathode terminal, or between the anode terminal and the cathode terminal of the PUT, an erroneous PUT cathode voltage signal will be produced. There is thus the problem that an erroneous delay output signal is produced, and hence the circuit is not fail-safe. This problem is even mentioned in Japanese Unexamined Patent Publication No. 2-141122.
In Japanese Unexamined Patent Publication No. 2-141122, in order to solve this problem, the cathode voltage signal and the gate voltage signal are respectively input to different self hold circuits, and the logical product output from the two self hold circuits is made the delay output signal. With such a circuit configuration, even if during timing after applying the input voltage V.sub.IN, a short circuit fault occurs between the gate terminal and the cathode terminal, there is no generation of an erroneous delay output signal. However with the circuit configuration of this conventional example, when the input signal V.sub.IN is cancelled, a capacitor for continually producing a differential signal is charged. Therefore, if the input signal V.sub.IN is applied in the condition with a short circuit fault occurring between the gate terminal and the cathode terminal of the PUT, there can be a problem of an erroneous delay output signal being produced having practically no delay time. Moreover there can be a problem in that, under conditions where the capacitor for setting the oscillation time constant of the PUT oscillation circuit has practically no charge, if a short circuit fault occurs simultaneously between the anode terminal and the gate terminal and the cathode terminal of the PUT, then when the input signal V.sub.IN is applied, the gate voltage signal will initially drop to become approximately a power source potential Vcc, after which it will rise. Therefore depending on the threshold value in an operational oscillator comprising a self hold circuit, there is the possibility of an erroneous delay output signal being produced.
With the circuit of Japanese Unexamined Patent Publication No. 2-141122, there is thus the problem that if a fault occurs in one of the constituent elements of the circuit, an erroneous delay output can be produced. Moreover, using two self hold circuits having operational oscillators causes an increase in cost, and is thus undesirable.
As is clear from the earlier discussion, when the beforementioned PUT oscillation circuit is operating normally, it changes from condition A to condition B and then returns again to condition A, while at the time of a fault, it remains in condition A or only changes from condition A to condition B. Therefore using these characteristics of an oscillation circuit, it is possible to verify if the PUT oscillation circuit is operating normally,
As a method for verifying normal operation of a PUT oscillation circuit using these characteristics, it has been considered to use for example the signal information of (1) and (2) below:
(1) a characteristic signal (voltage or current) condition produced only when the PUT oscillation circuit is operating normally, that is to say changes from condition A to condition B and then again to condition A (normal oscillation operation). PA1 (2) a sequential change in the voltage and current condition of the various parts of the circuit due to the PUT oscillation circuit operating normally, that is to say changing from condition A to condition B and then again to condition A (normal oscillation operation).
The present invention takes into consideration the above situation with the object of providing a fail-safe timing circuit which does not produce an erroneous timing output at the time of a fault, by providing a monitoring circuit for verifying if an oscillation circuit is operating normally by monitoring a voltage signal change condition which is based on the operating characteristics of the oscillation circuit. Moreover it is an object of the invention to provide a fail-safe on-delay circuit which does not produce an erroneous delay output at the time of a fault, by combining a logical product circuit with the fail-safe timing circuit.